A solid-state image sensor using a column analog to digital converter (A/D converter) reads a voltage signal, which depends on the intensity of received light, from each row of a pixel array and converts the voltage signal from analog to digital form from one row to another. In the analog to digital conversion (AD conversion or ADC), a lamp voltage signal indicating a voltage that linearly increases due to accumulating charge in a capacitor using a constant current source is generated, and the generated lamp voltage signal is compared with a read pixel voltage signal. A digital value depending on the read pixel voltage may be obtained as a count value of a counter by measuring a length of time that it takes for a voltage of the lamp voltage signal (“lamp voltage”) to become equal to or exceed a voltage of the read pixel voltage signal (“read pixel voltage”).
FIG. 1 illustrates a configuration of the column A/D converter. The column A/D converter in FIG. 1 includes an ADC determination circuit 10, an AND circuit 11, 1-bit counters 12-1 to 12-4, latches 13-1 to 13-4, and a shift register 14. Column A/D converters configured substantially the same as the column A/D converter in FIG. 1 are provided in the pixel array and each of the column A/D converters is arranged in each row of the pixel array. For example, the column A/D converter in FIG. 1 is an A/D converter that outputs a 4-bit digital value.
The read pixel voltage is applied to the ADC determination circuit 10. The ADC determination circuit 10 compares the lamp voltage signal with the read pixel voltage signal. When the lamp voltage is equal to or exceeds the read pixel voltage, the ADC determination circuit 10 allows an output signal to transition from a high state to a low state. The AND circuit 11 supplies the 1-bit counter 12-1 with an ADC clock while an output of the ADC determination circuit 10 is in the high state. The AND circuit 11 stops supplying the ADC clock to the 1-bit counter 12-1 when the output of the ADC determination circuit 10 transitions to the low state. At the time at which operations for the AD conversion start, the timing at which the AND circuit 11 starts outputting the clock signals is set to correspond to the timing at which the voltage of the lamp voltage signal starts to increase.
The 1-bit counter 12-1 receives the ADC clock as an input and performs a toggle operation. The 1-bit counter 12-2 receives an output of the 1-bit counter 12-1 as an input and performs a toggle operation. The 1-bit counter 12-3 receives an output of the 1-bit counter 12-2 as an input and performs a toggle operation. The 1-bit counter 12-4 receives an output of the 1-bit counter 12-3 as an input and performs a toggle operation. As a result, the 1-bit counters 12-1 to 12-4 operate as a 4-bit counter. Since the time that it takes for the AND circuit 11 to stop supplying the ADC clock is proportional to the read pixel voltage, the count value of the 4-bit counter is a digital value obtained through the AD conversion of the read pixel voltage. The 4-bit digital value is stored in the latches 13-1 to 13-4 at a desired timing. The shift register 14 selectively couples the latches 13-1 to 13-4 to buses Bus0 to Bus3.
FIG. 2 is a diagram illustrating signal timing relative to operations of the column A/D converter in FIG. 1. In FIGS. 2, 2A represents a clock signal for a count of the ADC (the ADC clock), 2B represents the output of the 1-bit counter 12-1 (bit0), 2C represents the output of the 1-bit counter 12-2 (bit1), 2D represents the output of the 1-bit counter 12-3 (bit2), 2E represents an output of the 1-bit counter 12-4 (bit3), 2F represents a count value of the 4-bit counter, and 2G represents a state of the latches 13-1 to 13-4.
The diagram in FIG. 2 illustrates a case where an input analog voltage (the read pixel voltage) has a highest value and the 4-bit digital value, after undergoing the AD, conversion is 15. The digital values represented by bits bit0 to bit3 are sequentially counted up when the bit bit0 is the least significant bit and the bit bit3 is the most significant bit. In this case, the count values indicated with 4 bits, namely, the bits bit0 to bit3 are synchronized with the ADC clock and increase from zero to 15. Each of the latches 13-1 to 13-4 holds a previous value while 2G in FIG. 2 indicates “Hold,” and latches current values of the bits bit0 to bit3 at the timing corresponding to the timing at which a highest count value is obtained, that is, the timing at which 2G in FIG. 2 indicates “Transfer.” In other words, the current values of the bits bit0 to bit3 are transferred to the buses as the latch outputs.
In the column A/D converter as described above, when the bit counts of the output digital values are considered to be fixed, increasing a frequency of the ADC clock may reduce time needed for capturing an image, which is called a “frame period,” by an amount corresponding to the increased frequency of the ADC clock. In other words, to achieve a desired frame period with a resolution of a desired AD conversion, that is, with a desired bit count, the frequency of the ADC clock needs to be higher than a certain degree. When high-speed captures of images with a high resolution are required, the ADC clock having a frequency high enough to satisfy such requirements needs to be used. However, in the A/D converter described above, the least significant 1-bit counter 12-1 is synchronized with a pulse of the ADC clock and performs a count operation. When the 1-bit counter 12-1 operates faster, influences of noises may grow and the accuracy of the AD conversion may be reduced. In another case, the frequency of the ADC clock higher than the frequency of the system clock may be needed and a circuit such as a phase-locked loop (PLL) circuit may be needed.